Field of Invention
The present invention relates to the field of semiconductor devices and their method of manufacture. More specifically, the invention provides an improved method of forming adjacent coplanar semiconductor devices, where the coplanar semiconductor devices require different semiconductor materials or different process steps for formation.
Description of the Prior Art
The earliest manufacturing processes for integrated circuit devices provided multiple identical devices formed on a single substrate using a single process sequence. In some cases it is desirable to form different devices on a single substrate. When forming different device structures on a single substrate, it is common to form device regions or islands within which different device structures are formed. Each device region or island is used for formation of different active or passive devices. The article Selective molecular-beam epitaxy for integrated npn/pnp heterojunction bipolar transistor applications, by Streit et al., J. Vac. Sci. Technology, Mar/Apr 1992, pages 1020-1022. shows the formation of two different device islands (a pnp island and an npn island) adjacent to each other. The pnp and npn device regions or islands act are used for formation of pnp and npn bipolar device structures.
FIG. 1 illustrates a fabrication sequence for the formation of two different device regions on a GaAs substrate. The term "different device regions" refers to formation of regions using different materials or process sequences. For example, although in the embodiment shown in FIG. 1 both devices regions are formed from the same semiconductor material (gallium arsenide) they have different dopant concentrations. Alternatively, the device regions could be formed using different materials. For example, the first device region could be comprised of gallium arsenide while the second device region is comprised of the group III-V alloy aluminum gallium arsenide. Further, the device regions can be comprised of a plurality of layers of different semiconductor materials.
FIG. 1A shows the resultant structure after formation of the active region of the first device type 102 on a gallium arsenide substrate 104, deposition of a dielectric layer 106, and patterning a well region 108 to define the active region of a second device structure. As shown in FIG. 1B, after formation of the well region 108, a layer of gallium arsenide 110 is deposited to form the active region of the second device. Although the gallium arsenide 110a deposited in well region 108 is monocrystalline, the gallium arsenide 110b grown on the surface of the dielectric 106 is polycrystalline.
The formation of a rough polycrystalline surface resulting from the growth of GaAs over a dielectric is well known. The articles GaAs planar technology by molecular beam epitaxy (MBE), A. Y. Cho, Journal of Applied Physics, Vol. 46, No. 2, February 1975, pgs. 783-785, and Lateral Definition of Monocrystalline GaAs Prepared by Molecular Beam Epitaxy, S. Hiyamizu et al., J. Electrochem. Soc.: Solid-State Science and Technology, July 1980, pgs. 1562-1567, both describe the growth of polycrystalline GaAs over an oxide region and monocrystalline GaAs growth over the opening of the GaAs substrate.
The formation of polycrystalline GaAs creates problems in the later formation of the second device region. First, the polycrystalline GaAs 110b forms a rough surface which decreases alignment accuracy in future masking steps. Another problem associated with the formation of polycrystalline GaAs 110b is the formation of dendrites 112 or whisker growth extending from the side of the polycrystalline GaAs layer 110b over the second device region 110a. Whisker growth can nucleate on the dielectric layer 106 and has been observed to extend out as much as 10 microns over the single-crystal window areas of the second device type thereby shadowing growth. The whisker growth makes it impossible to grow good quality GaAs near the interface between the first and second device regions 102, 110a making the area near the interface unusable. Further, adatom migration off of the dielectric into the active region of the second device has been observed, resulting in nonuniform composition or thickness near the sidewall of the well region. In addition, the shadowing effect of the whisker growth results in uneven thickness of the second GaAs deposition 110a near the interface between the first and second device regions.
After deposition of the gallium arsenide layer 110, the dielectric layer 106 and the polycrystalline GaAs layer 110b are removed to leave two coplanar device regions, Attempts to remove the polycrystalline GaAs layer 110b and the dielectric layer 106 by applying an etchant to the dielectric layer 106 have proved unreliable. The most reliable method for removing the polycrystalline GaAs layer 110b is by the remasking process illustrated in FIGS. 1C and 1D. Although remasking can be used to form adjacent coplanar device regions, there are problems associated with the remasking process, First, the remasking process adds additional steps to the device formation process including an alignment step which increases process complexity. Further, the remasking process increases the unusable portion of layer 110a near the interface between the first and second device regions.
Referring to FIG. 1C, a layer of photoresist is applied and alter alignment exposed to provide a mask 116 to protect the second device region 110a. Because of the whisker growth 112 formation extending over the second device region 110a, the mask 116 needed to remove the polycrystalline GaAs 110b is smaller in size than the mask used to form the well region of the second device. Thus a new mask is needed, increasing process costs. An etchant is applied to remove the polycrystalline GaAs 110b and the dielectric layer 106 in regions not protected by the mask 116. After the etch is complete, the first and second device regions 102, 110a remain as shown in FIG. 1D. However, because the mask 116 is decreased in size because of the polycrystalline dendrite 112 formation, there are unusable regions near the interface between the first and second device regions.
An improved method for formation of adjacent coplanar semiconductor devices which decreases process complexity and minimizes the unusable semiconductor regions near the interface between the two device types is needed.